DPSpice

Medium: Topology-independent dynamic phasor simulator
Tools: Python, C++, Rust, WebAssembly
Year: 2024 to 2026

A switching converter runs at tens of kilohertz. To watch its control loop settle over a single second, a classical simulator has to step through every one of those switching cycles, because stepping through time is the only thing it knows how to do. That is the reason detailed power-electronics simulation stops being useful exactly where system-level questions start.

The idea, and the part that was missing

Dynamic phasors get around this by tracking the slowly-varying envelope of each oscillation rather than the oscillation itself. A carrier that takes fifty thousand steps a second to resolve becomes an envelope that barely moves, and the solver steps at the speed of the thing you actually wanted to watch.

None of that is new. What was missing was a simulator you could hand an ordinary netlist to. Existing dynamic-phasor work derives the model by hand, per topology, which means the method only reaches circuits somebody has already sat down and reformulated. Change a component and the derivation starts again.

DPSpice takes the netlist instead. It parses the circuit, stamps a modified nodal analysis system, chooses a solver, and runs it. Netlist in, result out, with no reformulation step in between. That is the whole claim of the paper, and it is what the word topology-independent in the title is carrying.

What it costs, honestly

On the series-RLC benchmark the dynamic-phasor solve reproduces the classical time-domain waveform to an NRMSE of 9e-5. The two curves are drawn on top of each other below and you cannot see the gap, which is the point of showing them together rather than quoting the number alone.

The speedup grows with the simulated horizon, because the cost of a phasor solve follows the envelope while the cost of a time-domain solve follows the carrier. Over a short window there is nothing to win and the method can be slower. Over a long one the gap opens by orders of magnitude.

The right-hand axis below carries numbers, and they should be read as a slope rather than as a score. Absolute speedups are machine-dependent, and on solves fast enough to be dominated by measurement noise they move between runs on the same machine. I do not quote a headline multiple anywhere on this site for that reason. The claim is that the curve rises. How high it sits is a property of whatever laptop it ran on.

Two panels. Left: the classical time-domain waveform and the DPSpice dynamic-phasor solve of a series-RLC resonance, overlaid and indistinguishable, labelled NRMSE 9.0e-05. Right: a log-log plot of speedup against simulated window, rising steadily from below one at ten carrier cycles to over a hundred at three thousand. — Series-RLC resonance. The phasor solve sits on top of the classical waveform, and the advantage grows with the horizon rather than being a fixed multiple. Both panels are real engine output. dpspice-ecce2026

Where it stands

The paper is accepted at IEEE ECCE 2026 as a lecture, in Vancouver this October, written with Cheng Zhang at the University of Manchester. The reference implementation is Apache-2.0, archived on Zenodo, and installs as a command-line tool in one line.

The engine has since grown past the paper, and the parts that are not published stay unpublished. What is on this page is what is in the public record.

Go and check

IEEE ECCE 2026: Topology-Independent Dynamic Phasor Simulation via Modified Nodal Analysis. Accepted, lecture session, Vancouver, October 2026.
10.5281/zenodo.21085058: Archived release of the reference implementation.
github.com/doyun-gu/dpspice-ecce2026: Source, examples, and the reproduction scripts. Apache-2.0.
dpspice.com: The engine's own site.